1. Technical Field
The present invention concerns a circuit for generating the reference voltage of the address buffer in a dynamic random access memory(DRAM), and more particularly a circuit which supplies a current to the terminal for forming the reference voltage, during low voltage of Vcc, and discharges a part of the current of the terminal for forming the reference voltage, during high voltage, so that the variation of the reference voltage is reduced and transient phenomena during the low voltage are eliminated, therein using a charging-up and discharging circuit.
2. Related Art
Generally, the circuit for generating the reference voltage of a DRAM is to distinguish the address information of the address buffer between a logic "1" signal and a logic "0" signal. Conventionally, there are mainly used the circuits according to FIGS. 1 and 2 of this drawings attached to the specification. Referring to FIGS. 1 and 2, the P MOS transistor M1 is in series with the N MOS transistor M2 that has a diode structure to determine the reference voltage.(see FIG. 1). The P MOS transistor M1 has a diode structure to adjust the reference voltage. However, such a kind of circuit has a drawback that the level of the reference voltage is susceptible to variations in the power supply voltage Vcc. On the other hand, the circuit according to FIG. 2 includes N,P MOS transistors M3, M4, and the diodes D1,D2 so that the N MOS transistor M4 as well as P MOS transistor M3 is turned ON by the voltage Vcc. Therefore, the P,N MOS transistors M3, M4 are always turned ON. According to this conventional circuit, the amount of the current is limited in the standby state, and the level of the reference voltage is determined by the threshold voltages of the two diodes D1, D2 and the ON-state resistance of the N MOS transistor M4. However, there occurs a problem that the level of the output voltage of Vcc is transiently changed (shooting) in low voltage region.